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White Electronic Designs
512Kx32 SRAM MODULE, SMD 5962-94611
FEATURES
Access Times of 70, 85, 100, 120ns Packaging * 68 lead, Hermetic CQFP (G2T)1, 22.4mm (0.880 inch) square. 4.57mm (0.180 inch) high (Package 509) Organized as 512Kx32, User Configurable as 1Mx16 or 2Mx8 Commercial, Industrial and Military Temperature Ranges TTL Compatible Inputs and Outputs 5V Power Supply Low Power CMOS
WS512K32-XXX
Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight * WS512K32-XG2TX1 - 8 grams typical
Note 1: Package Not Recommended for New Designs. This product is subject to change without notice.
FIGURE 1 - PIN CONFIGURATION FOR WS512K32-XG2TX1
TOP VIEW
NC A0 A1 A2 A3 A4 A5 CS#3 GND CS#4 WE#1 A6 A7 A8 A9 A10 VCC
PIN DESCRIPTION
I/O0-31 A0-18 WE#1-4 CS#1-4 OE# VCC GND NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
BLOCK DIAGRAM
W E # 1 CS#1 OE# A0-18 W E # 2 CS#2 W E # 3 CS#3 W E # 4 CS#4
A16 CS#1 OE# CS#2
A17 WE#2 WE#3 WE#4
A12
A13
A14
A15
VCC
A18
A11
NC NC
512K x 8
512K x 8
512K x 8
512K x 8
8
8
8
8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
Note 1: Package Not Recommended for New Designs.
March 2005 Rev. 4
1
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Symbol TA TSTG VG TJ VCC -0.5 Min -55 -65 -0.5 Max +125 +150 VCC+0.5 150 7.0 Unit C C V C V
WS512K32-XXX
CAPACITANCE
TA = +25C
Parameter Symbol Conditions Max Unit OE# capacitance COE VIN = 0 V, f = 1.0 MHz 50 pF WE#1-4 capacitance CWE VIN = 0 V, f = 1.0 MHz 15 pF CQFP G2T CS#1-4 capacitance CCS VIN = 0 V, f = 1.0 MHz 20 pF Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 20 pF Address input capacitance CAD VIN = 0 V, f = 1.0 MHz 50 pF This parameter is guaranteed by design but not tested.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp (Mil) Symbol VCC VIH VIL TA Min 4.5 2.2 -0.5 -55 Max 5.5 VCC + 0.3 +0.8 +125 Unit V V V C
LOW CAPACITANCE CQFP
TA = +25C
Parameter OE# capacitance CQFP G4 capacitance CS#1-4 capacitance Symbol COE CWE CCS CI/O CAD Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Max Unit 32 32 15 15 32 pF pF pF pF pF
TRUTH TABLE
CS# H L L L OE# X L H X WE# X H H L Mode Standby Read Out Disable Write Data I/O High Z Data Out High Z Data In Power Standby Active Active Active
Data I/O capacitance Address input capacitance
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Input Leakage Current Output Leakage Current Operating Supply Current x 32 Mode Standby Current Output Low Voltage Output High Voltage NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V Symbol ILI ILO ICC x 32 ISB VOL VOH Conditions VCC = 5.5, VIN = GND to VCC CS# = VIH, OE# = VIH, VOUT = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 IOL = 2.1mA, VCC = 4.5 IOH = -1.0mA, VCC = 4.5 2.4 Min Max 10 10 200 4.0 0.4 Units A A mA mA V V
DATA RETENTION CHARACTERISTICS
(TA = -55C to +125C)
Parameter Data Retention Supply Voltage Data Retention Current Symbol VDR ICCDR1 Conditions CS# VCC -0.2V VCC = 3V Min 2.0 0.4 Typ Max 5.5 1.6 Units V mA
March 2005 Rev. 4
2
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
AC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, TA = -55C to +125C
Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z 1. This parameter is guaranteed by design but not tested. Symbol tRC tAA tOH tACS tOE tCLZ1 tOLZ1 tCHZ1 tOHZ1 10 5 25 25 5 70 35 10 5 25 25 -70 Min 70 70 5 85 40 10 5 Max Min 85 85 5 -85 Max Min 100 -100
WS512K32-XXX
-120 Max 100 5 100 50 10 5 35 35 35 35 120 60 Min 120 120 Max
Units ns ns ns ns ns ns ns ns ns
AC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, TA = -55C to +125C
Parameter Write Cycle Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold from Write Time 1. This parameter is guaranteed by design but not tested. Symbol tWC tCW tAW tDW tWP tAS tAH tOW1 tWHZ1 tDH 0 -15* Min 70 60 60 30 50 0 5 5 25 0 Max Min 85 75 75 30 50 0 5 5 25 0 -17 Max Min 100 80 80 40 60 0 5 5 35 0 -20 Max Min 120 100 100 40 60 0 5 5 35 -25 Max Units ns ns ns ns ns ns ns ns ns ns
FIGURE 2 - AC TEST CIRCUIT
Parameter
AC TEST CONDITIONS
Typ VIL = 0, VIH = 3.0 5 1.5 Unit V ns V Input Pulse Levels
Current Source
IOL
Input Rise and Fall Input and Output Reference Level
D.U.T. Ceff+50pf
VZ 1.5V (Bipolar Supply)
Output Timing Reference Level 1.5 V NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
Current Source
IOH
March 2005 Rev. 4
3
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIGURE 3 - TIMING WAVEFORM - READ CYCLE
WS512K32-XXX
tRC ADDRESS
tRC ADDRESS tAA
CS#
tAA
tACS
tCHZ
tOH DATA I/O PREVIOUS DATA VALID DATA VALID
OE#
tCLZ tOE tOLZ DATA I/O HIGH IMPEDANCE
tOHZ DATA VALID
READ CYCLE 1 (CS# = OE# = VIL, WE# = VIH)
READ CYCLE 2 (WE# = VIH)
FIGURE 4 - WRITE CYCLE - WE# CONTROLLED
tWC ADDRESS tAW tCW CS# tAS WE# tWHZ DATA I/O tDW tWP tOW tDH tAH
DATA VALID WRITE CYCLE 1, WE# CONTROLLED
FIGURE 5 - WRITE CYCLE - CS# CONTROLLED
tWC ADDRESS tAW tAS CS# tWP WE# tDW DATA I/O DATA VALID WRITE CYCLE 2, CS# CONTROLLED tDH tCW tAH
March 2005 Rev. 4
4
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WS512K32-XXX
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)1
25.15 (0.990) 0.26 (0.010) SQ 22.36 (0.880) 0.26 (0.010) SQ 4.57 (0.180) MAX 0.27 (0.011) 0.04 (0.002)
0.25 (0.010) REF
24.03 (0.946) 0.26 (0.010) 1 / 7
R 0.25 (0.010) 0.19 (0.007) 0.06 (0.002)
1.0 (0.040) 0.127 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP 0.38 (0.015) 0.05 (0.002)
SEE DETAIL "A"
20.3 (0.80) REF
Note 1: Package Not Recommended for New Designs. ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
March 2005 Rev. 4
5
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION
WS512K32-XXX
W S 512K 32 - XXX X X X
LEAD FINISH: Blank = Gold plated leads A = Solder dip leads
DEVICE GRADE: Q M I C = MIL-STD-883 Compliant = Military Screened = Industrial = Commercial -55C to +125C -40C to 85C 0C to +70C
PACKAGE TYPE: G2T1 = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 509)
ACCESS TIME (ns) ORGANIZATION, 512Kx32 User configurable as 1Mx16 or 2Mx8 SRAM WHITE ELECTRONIC DESIGNS CORP.
Note 1: Package Not Recommended for New Designs.
DEVICE TYPE 512K x 32 SRAM Module 512K x 32 SRAM Module 512K x 32 SRAM Module 512K x 32 SRAM Module
SPEED 120ns 100ns 85ns 70ns
PACKAGE 68 lead CQFP (G2T) 68 lead CQFP (G2T) 68 lead CQFP (G2T) 68 lead CQFP (G2T)
1 1 1 1
SMD NO. 5962-94611 01HMX 5962-94611 02HMX 5962-94611 03HMX 5962-94611 04HMX
March 2005 Rev. 4
6
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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